About

AMD's Ryzen architecture relies heavily on the Infinity Fabric (FCLK) speed, which connects the CPU cores to the I/O die. Optimal performance occurs when the Memory Controller (UCLK) and Infinity Fabric run in a 1:1 synchronous ratio with the Memory Frequency (MCLK). Decoupling these ratios introduces a significant latency penalty (approx. 10ns), negating the benefits of higher raw frequency.

This tool is designed to solve the unique challenges of Ryzen memory tuning. Unlike Intel, Ryzen platforms are highly sensitive to impedance terminations (ProcODT, RTT_NOM, RTT_PARK). Incorrect resistance values often lead to "boot loops" or silent data corruption. This calculator provides verified impedance configurations and timing sets based on the AGESA codebase limitations for Zen+ (Ryzen 2000), Zen 2 (Ryzen 3000), and Zen 3 (Ryzen 5000) architectures.

Formulas

For AMD Ryzen systems, optimal latency is achieved when the coupled mode is active:

FCLK : UCLK : MCLK = 1 : 1 : 1

If MCLK exceeds the silicon stability limit of FCLK, the system incurs a penalty. The termination resistance (ProcODT) is critical for signal integrity, typically measured in Ohms (Ω). The theoretical signal reflection minimization follows transmission line theory where source and load impedance match.

Reference Data

CPU Family	Max FCLK (Avg)	Ideal 1:1 Memory Freq	Typical ProcODT	Topology
Zen (Ryzen 1000)	N/A	2933 - 3200 MHz	53.3 - 60 Ω	Daisy Chain / T-Top
Zen+ (Ryzen 2000)	N/A	3200 - 3466 MHz	48 - 53.3 Ω	Daisy Chain
Zen 2 (Ryzen 3000)	1800 - 1900 MHz	3600 - 3800 MHz	36.9 - 43.6 Ω	Daisy Chain
Zen 3 (Ryzen 5000)	1900 - 2000 MHz	3800 - 4000 MHz	34.3 - 40 Ω	Daisy Chain
Zen 3 APU (5000G)	2200+ MHz	4400+ MHz	40 Ω	Monolithic
Samsung B-Die	N/A	Scale w/ Voltage	Low RTT_PARK	IC Specific
Micron Rev. E	N/A	High Freq Capable	High RTT_PARK	IC Specific
Hynix CJR/DJR	N/A	Medium Scaling	Mixed	IC Specific

Frequently Asked Questions

For Zen 2 and Zen 3, the target is 3600MHz to 3800MHz RAM speed with an Infinity Fabric (FCLK) of 1800MHz to 1900MHz respectively. This maintains the 1:1 ratio. Going above 3800MHz usually desynchronizes the fabric (2:1 mode), causing latency to jump from ~55ns to ~75ns.

Ryzen platforms are sensitive to ProcODT. If 36.9 Ohms fails, try the next step up (40 Ohms or 43.6 Ohms). Also, ensure your DRAM Voltage (VDIMM) matches the preset (usually 1.35V to 1.45V) and SoC Voltage is sufficient (1.05V - 1.125V).

Gear Down Mode effectively allows the memory to latch commands on every other clock edge, similar to a 1.5T command rate. It significantly improves stability for odd CAS latencies (e.g., CL15 becomes CL16 technically) and high frequencies. It is recommended to leave it Enabled for stability.

You can use software tools like Thaiphoon Burner to read the SPD data of your memory sticks. Knowing if you have B-die, E-die, or CJR is essential as they require vastly different timings and resistance settings.