About

For users who prefer manual BIOS tuning over XMP profiles, ensuring mathematical consistency between timing parameters is crucial for OS stability. Entering random numbers often results in immediate POST failure or subtle memory corruption that appears as application crashes days later.

This tool acts as a validation engine. It takes your primary timings and validates them against JEDEC standard rules and common overclocking ratios. It specifically checks critical relationships, such as ensuring tRAS provides enough time for a row close command after an activate command, preventing physical data loss in the memory cells.

Formulas

The core stability formula for DDR4 ensures the row remains open long enough to complete operations:

tRAS ≥ tCL + tRCD + 2

The total Row Cycle Time includes the precharge time:

tRC ≥ tRAS + tRP

Reference Data

Timing	Full Name	Formula / Rule of Thumb	Min Safe (ns)
tCL	CAS Latency	Base reference	~7.5 ns
tRCD	RAS to CAS Delay	tCL to tCL + 4	~8.0 ns
tRAS	Row Active Time	tCL + tRCD + 2	~21 ns
tRC	Row Cycle Time	tRAS + tRP	~45 ns
tRFC	Refresh Cycle Time	160ns (B-die) to 350ns	120 ns
tFAW	Four Activate Window	4 × tRRD_S	16 (ticks)

Frequently Asked Questions

If tRAS is lower than tCL + tRCD, the memory controller might close the row before the data has been fully read or written. This leads to data corruption (files changing hashes) or blue screens (BSOD).

These are mathematically safe minimums based on your inputs. However, your physical RAM stick quality determines if it can actually run these speeds. Always run a memory stress test (like TM5 or HCI Memtest) after changing timings.

tRFC is the Refresh Cycle Time. It is the time required to recharge the capacitors in the RAM. It is measured in hundreds of clock cycles. Setting this too low is the #1 cause of cold-boot issues.

It generates a compact text block of your configuration that you can share on forums (like Reddit r/overclocking) or save to a notepad file for backup.