Binary Bitwise NOR Calculator
Calculate binary bitwise NOR operations on two binary numbers. Get instant NOR results with decimal conversion, truth table, and step-by-step breakdown.
| Bit # | A | B | A OR B | NOR |
|---|
About
The NOR gate is a universal logic gate. Any Boolean function can be constructed using only NOR operations, making it foundational in digital circuit design. The NOR of two bits A and B equals NOT(A OR B). It outputs 1 only when both inputs are 0. Miscalculating a single NOR bit in a hardware description language propagates errors through entire adder or multiplexer chains. This tool operates on binary strings up to 64 bits, automatically zero-pads operands to equal length, and returns both the binary result and its decimal equivalent.
Note: this calculator assumes unsigned integer representation. Two's complement signed interpretation is not applied. For inputs exceeding 64 bits, truncation occurs at the most significant end. Pro Tip: verify NOR results against AND/OR/NOT decompositions when debugging multi-gate circuits - a single inverted bit in a NOR cascade can flip an entire bus line.
Formulas
The bitwise NOR operation processes two binary operands bit by bit. For each bit position i, the result bit Ri is computed as follows:
This is equivalent to the following piecewise definition:
The full result is the concatenation of all Ri from the most significant bit to the least significant bit. Operands are zero-padded on the left to match the length of the longer operand before computation. Decimal conversion uses positional notation:
Where Ai is the i-th bit of operand A, Bi is the i-th bit of operand B, Ri is the i-th bit of the result, n is the total number of bits after padding, bi is the bit value at position i (from LSB), and D is the unsigned decimal equivalent.
Reference Data
| Gate | Symbol | Expression | Output when A=0,B=0 | Output when A=0,B=1 | Output when A=1,B=0 | Output when A=1,B=1 | Universal? |
|---|---|---|---|---|---|---|---|
| AND | ∧ | A ⋅ B | 0 | 0 | 0 | 1 | No |
| OR | ∨ | A + B | 0 | 1 | 1 | 1 | No |
| NOT | ¬ | ¬A | 1 | Unary operator | No | ||
| NAND | ¬∧ | ¬(A ⋅ B) | 1 | 1 | 1 | 0 | Yes |
| NOR | ¬∨ | ¬(A + B) | 1 | 0 | 0 | 0 | Yes |
| XOR | ⊕ | A ⊕ B | 0 | 1 | 1 | 0 | No |
| XNOR | ¬⊕ | ¬(A ⊕ B) | 1 | 0 | 0 | 1 | No |
| Buffer | → | A | 0 | Passes input | No | ||
| NOR (3-input) | ¬∨ | ¬(A+B+C) | 1 only when all inputs are 0 | Yes | |||
| NOT via NOR | ¬ | A NOR A | 1 | 0 | 0 | 0 | - |
| OR via NOR | ∨ | (A NOR B) NOR (A NOR B) | 0 | 1 | 1 | 1 | - |
| AND via NOR | ∧ | (A NOR A) NOR (B NOR B) | 0 | 0 | 0 | 1 | - |
| CMOS NOR | - | 2 PMOS series + 2 NMOS parallel | Transistor count: 4 | - | |||
| TTL 7402 | - | Quad 2-input NOR | Supply: 4.75 - 5.25 V | - | |||
| ECL NOR | - | Emitter-coupled logic | Propagation delay: <1 ns | - | |||