About

The NAND (Not-AND) gate is a universal gate in digital logic. Any Boolean function can be constructed entirely from NAND gates, making it the foundational building block of modern processors and memory circuits. The operation takes two binary operands A and B, computes the bitwise AND, then inverts every bit of the result. A single miscalculated bit in a NAND chain propagates errors through an entire circuit design. This tool performs the operation with full bit-position breakdown so you can verify intermediate AND values before the final inversion, matching what happens at the transistor level.

Inputs are zero-padded to a selectable word size (4, 8, 16, or 32 bits). The tool assumes unsigned integers only. Overflow is handled by truncation to the chosen word size. Results are displayed in binary, decimal, hexadecimal, and octal representations. Pro tip: when debugging combinational logic in HDL or breadboard prototypes, verify your expected NAND outputs here before committing to silicon or FPGA bitstream.

Formulas

The NAND operation is the negation of bitwise AND. For two n-bit unsigned integers A and B:

Y = ¬(A ∧ B)

In two's complement representation with a mask M = 2ⁿ − 1, the implementation is:

Y = (¬(A ∧ B)) ∧ M

The mask ensures the result stays within the n-bit word size by zeroing out higher bits that JavaScript's 32-bit signed integer NOT operator would set. For each bit position i from 0 to n − 1:

Y_i = ¬(A_i ∧ B_i)

Where A_i is the bit at position i of operand A, B_i is the bit at position i of operand B, Y_i is the resulting bit, n is the word size in bits, and M is the bitmask for the word size.

Reference Data

A	B	A ∧ B (AND)	¬(A ∧ B) (NAND)
0	0	0	1
0	1	0	1
1	0	0	1
1	1	1	0

Gate	Symbol	Boolean Expression	Universality	Transistor Count (CMOS)	Propagation Delay (typ.)
NAND	¬(A ⋅ B)	Y = ¬(A ∧ B)	Universal	4	1.2 ns
AND	A ⋅ B	Y = A ∧ B	Not universal	6	1.8 ns
OR	A + B	Y = A ∨ B	Not universal	6	1.8 ns
NOR	¬(A + B)	Y = ¬(A ∨ B)	Universal	4	1.2 ns
NOT	¬A	Y = ¬A	Not universal	2	0.6 ns
XOR	A ⊕ B	Y = A ⊕ B	Not universal	8	2.4 ns
XNOR	¬(A ⊕ B)	Y = ¬(A ⊕ B)	Not universal	8	2.4 ns
Buffer	A	Y = A	Not universal	4	1.2 ns
NOT via NAND	NAND(A,A)	Y = ¬A	-	4	1.2 ns
AND via NAND	NAND(NAND(A,B))	Y = A ∧ B	-	8	2.4 ns
OR via NAND	NAND(NAND(A,A),NAND(B,B))	Y = A ∨ B	-	12	3.6 ns

Frequently Asked Questions

Any Boolean function (AND, OR, NOT, XOR, NOR, XNOR) can be constructed using only NAND gates. A NOT gate is a NAND with both inputs tied together: Y = NAND(A, A). An AND gate requires two NANDs: first compute NAND(A, B), then NOT the result. An OR gate requires three NANDs: NOT each input, then NAND the results. This universality is why CMOS fabrication heavily relies on NAND structures.

Inputs shorter than the selected word size are left-padded with zeros. For example, input 101 in 8-bit mode becomes 00000101. The NAND of two zero-padded high bits yields 1, since NAND(0, 0) = 1. This means a wider word size produces more leading 1s in the result. Always match the word size to your target architecture to avoid misinterpretation.

The calculator truncates the input to the rightmost n bits of the selected word size. For instance, entering a 10-bit number in 8-bit mode discards the two most significant bits. This mirrors hardware behavior where register overflow silently drops high-order bits. A validation warning is displayed when truncation occurs.

Both are universal gates with identical CMOS transistor counts (4 transistors each). The difference is electrical: NAND gates use PMOS transistors in parallel and NMOS in series, favoring pull-up speed. NOR gates use the inverse topology, favoring pull-down speed. In practice, NAND gates are faster in most CMOS processes because PMOS parallel networks have lower effective resistance. This is why NAND flash memory and most standard cell libraries default to NAND-based implementations.

This tool operates on unsigned binary representations. For signed (two's complement) numbers, the bitwise NAND operation is identical at the bit level, but the decimal interpretation of the result differs. If you need signed output, take the binary NAND result, check the MSB (most significant bit): if it is 1, the signed decimal value equals the unsigned value minus 2ⁿ, where n is the word size.

NAND is NOT-AND. AND(0, 0) = 0. Negating 0 gives 1. This is consistent with the Boolean truth table. In fact, NAND returns 0 only when both inputs are 1. This property makes NAND the complement of AND and is the basis for its use in memory latch circuits (SR latches) where the default resting state is logic high.