About

Binary addition is the foundation of every arithmetic logic unit (ALU) in digital processors. Two operands of arbitrary bit-length are summed column by column from the least-significant bit (LSB) to the most-significant bit (MSB), propagating a carry c at each stage. A single mishandled carry bit in hardware design or firmware can cascade into catastrophic miscalculation - buffer overflows, checksum failures, and data corruption all trace back to this primitive operation. This tool implements a full-adder chain: for each bit position i, the sum bit s_i and carry-out c_i+1 are computed from inputs a_i, b_i, and carry-in c_i. Results are cross-verified with arbitrary-precision integer arithmetic. The tool assumes unsigned integers with no fixed word size - the output grows to accommodate any carry-out from the MSB.

Formulas

The full-adder computes, for each bit position i, a sum bit and a carry-out from three single-bit inputs: operand bit a_i, operand bit b_i, and carry-in c_i.

s_i = a_i ⊕ b_i ⊕ c_i

c_i+1 = (a_i ∧ b_i) ∨ (c_i ∧ (a_i ⊕ b_i))

Where ⊕ is the XOR (exclusive-or) gate, ∧ is AND, and ∨ is OR. The initial carry c₀ = 0. The process iterates from i = 0 (LSB) to i = n − 1 (MSB), where n is the length of the longer operand. If the final carry c_n = 1, the result has n + 1 bits. The decimal equivalent of any binary number is computed as the positional sum: D = n−1∑i=0 b_i ⋅ 2ⁱ.

Reference Data

a	b	c_in	s (Sum)	c_out (Carry)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1
Common Binary Addition Examples
1010 + 0110		10000 (decimal 10 + 6 = 16)
1111 + 0001		10000 (decimal 15 + 1 = 16)
1100 + 1100		11000 (decimal 12 + 12 = 24)
101010 + 010101		111111 (decimal 42 + 21 = 63)
11111111 + 1		100000000 (decimal 255 + 1 = 256)
Standard Word Sizes
Nibble		4 bits - max value 1111 (15)
Byte		8 bits - max value 11111111 (255)
Word (16-bit)		16 bits - max value 65535
Double Word		32 bits - max value 4294967295
Quad Word		64 bits - max value 18446744073709551615
Powers of 2
2⁰		1
2¹		2
2²		4
2³		8
2⁴		16
2⁵		32
2⁶		64
2⁷		128
2⁸		256
2¹⁰		1024
2¹⁶		65536
2³²		4294967296

Frequently Asked Questions

When the final carry-out c_n equals 1, the result requires one additional bit. For example, 1111 + 0001 = 10000 - a 4-bit addition yielding a 5-bit result. In fixed-width hardware (e.g., an 8-bit register), this is an overflow condition. This tool uses arbitrary-length operands, so the output always grows to accommodate the carry. No truncation occurs.

In a ripple-carry adder, the worst-case delay is proportional to the number of bits n, because each carry must propagate through every full-adder stage. The critical path is n gate-delays long. Real processors use carry-lookahead adders (CLA) that compute carries in log₂(n) stages by pre-computing generate (g = a ∧ b) and propagate (p = a ⊕ b) signals. This tool visualizes the ripple-carry model for educational clarity.

Yes. The shorter operand is implicitly zero-padded on the left (MSB side) to match the length of the longer operand. For example, adding 11 (2 bits) to 10101 (5 bits) treats the first operand as 00011. The step-by-step visualization shows this padding explicitly.

XOR (⊕) returns 1 when exactly one of its two inputs is 1, and 0 otherwise. Its truth table is identical to single-bit addition without carry: 0+0=0, 0+1=1, 1+0=1, 1+1=0. The carry is then handled separately by the AND gate. The full-adder chains XOR twice: once for a ⊕ b, then for the intermediate result ⊕ c_in.

Convert both operands to decimal, add them, then convert the decimal sum back to binary. This tool performs this cross-check automatically using arbitrary-precision arithmetic (BigInt). If the bitwise full-adder result and the BigInt verification disagree, a discrepancy warning appears - though this should never happen for valid unsigned binary inputs.

Yes. Leading zeros are preserved in the step-by-step visualization for alignment but stripped from the final result. Input 00101 is treated as 101 (decimal 5). The decimal conversion ignores leading zeros.